BPB Online LLP
Hardware Description Language Demystified
Hardware Description Language Demystified
US$ 19.95
The publisher has enabled DRM protection, which means that you need to use the BookFusion iOS, Android or Web app to read this eBook. This eBook cannot be used outside of the BookFusion platform.
Description
Contents
Reviews

Get familiar and work with the basic and advanced Modeling types in Verilog HDL

Key Features
Learn about the step-wise process to use Verilog design tools such as Xilinx, Vivado, Cadence NC-SIM
Explore the various types of HDL and its need
Learn Verilog HDL modeling types using examples
Learn advanced concept such as UDP, Switch level modeling
Learn about FPGA based prototyping of the digital system

Description
Hardware Description Language (HDL) allows analysis and simulation of digital logic and circuits. The HDL is an integral part of the EDA (electronic design automation) tool for PLDs, microprocessors, and ASICs. So, HDL is used to describe a Digital System. The combinational and sequential logic circuits can be described easily using HDL. Verilog HDL, standardized as IEEE 1364, is a hardware description language used to model electronic systems.

This book is a comprehensive guide about the digital system and its design using various VLSI design tools as well as Verilog HDL. The step-wise procedure to use various VLSI tools such as Xilinx, Vivado, Cadence NC-SIM, is covered in this book. It also explains the advanced concept such as User Define Primitives (UDP), switch level modeling, reconfigurable computing, etc. Finally, this book ends with FPGA based prototyping of the digital system.

By the end of this book, you will understand everything related to digital system design.

What will you learn
Implement Adder, Subtractor, Adder-Cum-Subtractor using Verilog HDL
Explore the various Modeling styles in Verilog HDL
Implement Switch level modeling using Verilog HDL
Get familiar with advanced modeling techniques in Verilog HDL
Get to know more about FPGA based prototyping using Verilog HDL

Who this book is for
Anyone interested in Electronics and VLSI design and want to learn Digital System Design with Verilog HDL will find this book useful. IC developers can also use this book as a quick reference for Verilog HDL fundamentals & features.

Table of Contents
1. An Introduction to VLSI Design Tools
2. Need of Hardware Description Language (HDL)
3. Logic Gate Implementation in Verilog HDL
4. Adder-Subtractor Implementation Using Verilog HDL
5. Multiplexer/Demultiplexer Implementation in Verilog HDL
6. Encoder/Decoder Implementation Using Verilog HDL
7. Magnitude Comparator Implementation Using Verilog HDL
8. Flip-Flop Implementation Using Verilog HDL
9. Shift Registers Implementation Using Verilog HDL
10. Counter Implementation Using Verilog HDL
11. Shift Register Counter Implementation Using Verilog HDL
12. Advanced Modeling Techniques
13. Switch Level Modeling
14. FPGA Prototyping in Verilog HDL

About the Author
Dr. Cherry Bhargava is working as an associate professor and head, VLSI domain, School of Electrical and Electronics Engineering at Lovely Professional University, Punjab, India. She has more than 14 years of teaching and research experience. She is Ph.D. (ECE), IKGPTU, M.Tech (VLSI Design & CAD) Thapar University and B.Tech (Electronics and Instrumentation) from Kurukshetra University. She is GATE qualified with All India Rank 428.
She has authored about 50 technical research papers in SCI, Scopus indexed quality journals, and national/international conferences.

Dr. Rajkumar Sarma received his B.E. in Electronics and Communications Engineering from Vinayaka Mission’s University, Salem, India & M.Tech degree from Lovely Professional University, Phagwara, Punjab and currently pursuing Ph.D. from Lovely Professional University, Phagwara, Punjab.

Language
English
ISBN
9789389898040
Cover Page
Title Page
Copyright Page
Dedication Page
About the Authors
Acknowledgement
Preface
Errata
Table of Contents
1. Introduction to VLSI Design Tools
Structure
Objectives
1.1 Xilinx ISE 9.2i
1.1.1. How to start the tool
1.1.2. Create a new project
1.1.3. Simulation using Xilinx ISE 9.2i
1.2. The VIVADO Design Suite
1.2.1. Creating a new project
1.2.2. Simulation of project
1.3 The Cadence NC-SIM
1.3.1. Creating a new project
1.3.2. Simulating the project
Conclusion
Questions
2. The Need for Hardware Description Language (HDL)
2.1. Introduction to HDL for digital circuits
Structure
Objectives
2.1.1. Need for Hardware Description Language (HDL)
2.2. VLSI Design flow
2.2.1. Digital system design using Verilog HDL
2.3. Modeling styles in Verilog HDL
2.3.1. Gate-level modeling
Verilog HDL using structural modeling/gate-level modeling
Verilog HDL for logic circuits with delays
2.3.2. Data flow modeling
Verilog code using data flow modeling
2.3.3. Behavioral modelling
Verilog code using behavioral modeling
2.3.4. Switch level modeling
Verilog code using switch level modeling
Conclusion
Questions
3. Logic Gate Implementation in Verilog HDL
3.1. Logic gates
Structure
Objectives
3.1.1. AND gate
3.1.1.1 Verilog program for two-input AND gate in dataflow modeling
3.1.1.2 Verilog program for two-input AND gate using structural modeling
3.1.1.3 Verilog program for two-input AND gate in behavioral modeling
3.1.1.4 Verilog program for two input AND gate in switch level modeling
3.1.2. OR gate
3.1.2.1 Verilog program for two-input OR gate in dataflow modeling
3.1.2.2 Verilog program for two-input OR gate in gate-level modeling
3.1.2.3 Verilog program for two input OR gate in behavioral modeling
3.1.2.4 Verilog program for two input OR gate in switch-level modeling
3.1.3. NOT gate
3.1.3.1 Verilog program for two input NOT gate in dataflow modeling
3.1.3.2 Verilog program for two input NOT gate in gate-level modeling
3.1.3.3 Verilog program for two input OR gate in behavioral modeling
3.1.3.4 Verilog program for two input NOT gate in switch-level modeling
3.2. Advanced logic gates
3.2.1. NAND gate
3.2.1.1 Verilog program for two input NAND gate in dataflow modeling
3.2.1.2 Verilog program for two input NAND gate in gate-level modeling
3.2.1.3 Verilog program for two input NAND gate in behavioral modeling
3.2.1.4 Verilog program for two input NAND gate in switch-level modeling
3.2.2 NOR gate
3.2.2.1 Verilog program for two input NOR gate in dataflow modeling
3.2.2.2 Verilog program for two input NOR gate in gate-level modeling
3.2.1.3 Verilog program for two input NAND gate in behavioral modeling
3.2.1.4 Verilog program for two input NOR gate in switch-level modeling
3.2.3. EX-OR or XOR gate
3.2.3.1 Verilog program for two input XOR gate in dataflow modeling
3.2.3.2 Verilog program for two input XOR gate in gate-level modeling
3.2.3.3 Verilog program for two input XOR gate in behavioral modeling
3.2.3.4 Verilog program for two input XOR gate in switch-level modeling
3.2.4. EX-NOR or XNOR gate
3.2.4.1 Verilog program for two input XNOR gate in dataflow modeling
3.2.4.2 Verilog program for two input XNOR gate in gate-level modeling
3.2.4.3 Verilog program for two input XNOR gate in behavioral modeling
3.2.4.4 Verilog program for two input XNOR gate in switch-level modeling
Conclusion
Questions
4. Adder-Subtractor Implementation Using Verilog HDL
4.1. Introduction
Structure
Objectives
4.2. The design strategy of combinational logic circuits
4.3. Adders
4.3.1. Half Adder
4.3.2. Full adder
4.3.3 Verilog program for half adder in dataflow modelling
4.3.4 Verilog program for full adder using half adder
4.4. Subtractor
4.4.1. Half subtractor
4.4.2. Full subtractor
4.4.3 Verilog program for half subtractor in behavioral modelling
4.4.4 Verilog program for full subtractor using half subtractor
4.4.5 Verilog program for full subtractor using half subtractor
4.5 . Verilog code for adder cum subtractor
Conclusion
Questions
5. Multiplexer/Demultiplexer Implementation in Verilog HDL
5.1 Introduction to multiplexer
Structure
Objectives
5.2 The 4:1 Multiplexer
5.3. IC 74153 pin diagram
5.4. Verilog program for 2:1 mux design
5.4.1. Multiplexer implementation using dataflow modeling
5.4.2. Multiplexer implementation using gate-level modelling
5.4.3. Multiplexer implementation using behavioral modeling
5.5. Verilog program for 4:1 mux design
5.5.1. Multiplexer implementation using dataflow modelling
5.5.2. Multiplexer implementation using structural modelling
5.6. Verilog program for 8:1 mux design
5.6.1. Multiplexer implementation using structural modelling
5.7. Introduction to demultiplxer
5.7. The 1:2 demultiplexer
5.8. The 1:4 demultiplexer
5.9. Verilog program for 1:2 demux design
5.9.1. Demultiplexer implementation using dataflow modelling
5.9.2. Demultiplexer implementation using gate-level modelling
5.9.3. Demultiplexer implementation using behavioral modelling
5.10. Verilog program for 1:4 demux design
5.10.1. Demultiplexer implementation using dataflow modelling
5.10.2. Demultiplexer implementation using gate-level modelling
5.11. Verilog program for 1:8 demux design
5.11.1. Demultiplexer implementation using behavioral modeling
Conclusion
Questions
6. Encoder/Decoder Implementation Using Verilog HDL
6.1. Introduction to encoder
Structure
Objectives
6.2. Octal to binary encoder
6.3. Decimal to BCD encoder
6.4. Verilog program for 4:2 encoder
6.4.1. The 4:2 encoder design using dataflow modeling
6.4.2. The 4:2 encoder design using behavioral modeling
6.5. Priority encoder
6.6. Verilog code for priority encoder design
6.7. Introduction to decoder
6.8. The 2 line to 4 line decoder
6.9. The 3 line to 8 line decoder
6.10. Verilog program for 2:4 decoder design
6.10.1. Decoder implementation using dataflow modelling
6.10.2. Decoder implementation using gate-level modelling
6.10.3. Decoder implementation using behavioral modelling
6.11. Verilog program for 3:8 decoder design
6.11.1. Decoder implementation using behavioral modelling
6.11.2. The 3:8 decoder implementation using 2:4 decoder
Conclusion
Questions
7. Magnitude Comparator Implementation Using Verilog HDL
7.1. Introduction
Structure
Objectives
7.2. One-bit magnitude comparator
7.2.1. One bit magnitude comparator using logic gates
7.3. Two-bit magnitude comparator
7.3.1. Two-bit magnitude comparator using logic gates
7.3.2. N-bit magnitude comparator using Verilog HDL
Conclusion
Questions
8. Flip-Flop Implementation Using Verilog HDL
8.1. Introduction to flip-flop
Structure
Objectives
8.1.1. Types of flip-flop
8.2. SR flip-flop
8.2.1. Characteristics table of SR flip-flop
8.2.2. Excitation table of SR flip-flop
8.3. JK flip-flop
8.3.1. Characteristics table of JK flip-flop
8.3.2. Excitation table of JK flip-flop
8.4. Master-slave JK flip-flop
8.4.1. Working of a master-slave flip-flop
8.5. D flip-flop
8.5.1. Characteristics table of D flip-flop
8.5.2. Excitation table of D flip-flop
8.6. T flip-flop
8.6.1. Characteristics table of T flip-flop
8.6.2. Excitation table of T flip-flop
Conclusion
Questions
9. Shift Registers Implementation Using Verilog HDL
9.1. Introduction to shift registers
Structure
Objectives
9.1.1 Classification of shift registers
9.2. Serial-In-Serial-Out (SISO) shift registe0r
9.3. Serial-In-Parallel-Out (SIPO) shift register
9.4. Parallel-In-Serial-Out (PISO) shift register
9.5. Parallel-In-Parallel-Out (PIPO) shift register
Conclusion
Questions
10. Counter Implementation Using Verilog HDL
10.1. Introduction to Counters
Structure
Objectives
10.1.1. Classification of counters
10.2. Asynchronous counters
10.2.1. MOD-4/2-bit asynchronous counter/ripple counter
10.2.2. Advantages & disadvantages of asynchronous counters
10.2.3. Verilog program of the 2-bit asynchronous counter using the positive edge-triggered T flip-flop
10.3. Synchronous counter
10.3.1. Mod-4/2-bit synchronous counter using JK flip-flop
10.3.2. 3-bit up/down counter using T flip-flop
10.3.3. Verilog program of 2-bit synchronous counter using positive edge triggered D flip-flop
10.3.4. Verilog program of 4-bit up/down counter in behavioural modelling
Conclusion
Questions
11. Shift Register Counter Implementation Using Verilog HDL
11.1. Introduction to shift register counters
Structure
Objectives
11.1.1 Types of shift register counters
11.1.1.1 Ring counter
11.1.1.2. Johnson counter
11.2. Count the number of ones in a bit sequence using Verilog HDL
11.2.1. Implementation using TASK
11.2.2. Implementation using FUNCTION
Conclusion
Questions
12. Advanced Modelling Techniques
12.1. Introduction to UDP
Structure
Objectives
12.1.1. Types of UDP
12.2. Syntax of UDP
12.3. Rules of UDP
12.4. Verilog HDL program using UDP
12.4.1. Verilog code for 4x1 multiplexer using UDP
12.4.2. Verilog code for JK flip-flop using UDP
Conclusion
Questions
13. Switch Level Modelling
13.1. Introduction to switch level modeling
Structure
Objectives
13.2. Switch level primitives
13.2.1.MOS switches
13.2.2. CMOS switches
13.3. Switch level modelling using Verilog HDL
13.3.1. Two-input NAND gate using PMOS/NMOS switches
13.3.2. Verilog HDL program in switch level modelling for implementing the logical expression, Y = AB + C
13.3.3. Verilog HDL program in switch level modelling (using TG) for implementing the logical expression, Y = AB + C
Conclusion
Questions
14. FPGA Prototyping in Verilog HDL
14.1. Introduction to HDL programming
Structure
Objectives
14.2. Programming FPGA board
14.3. Example of digital design on Nexys-4 Artix-7 FPGA board
14.3.1. Half adder
14.3.2. HDL source file
14.3.3. HDL top module
14.3.4. XDC file
Conclusion
Questions

Loading...