Free Range VHDL

Free Range VHDL

By Fabrizio Tappero
Book Description

This book is a fundamental guide to develop the skills necessary to write powerful VHDL code.

The approach taken by this book is to provide only what you need to know to get up and running quickly in VHDL. As with all learning, once you have obtained and applied some useful information, it is much easier to build on what you know as opposed to continually adding information that is not directly applicable to the subjects at hand.

VHDL is an extremely powerful tool. The more you understand as you work and study with VHDL, the more it will enhance your learning experience independently of your particular area of interest. The concept of using software to design hardware that is controlled by software will definitely provide you with endless hours of contemplation.

This book was written with the intention of being freely available to everybody. A paperback version can be purchased from our on-line store.

Table of Contents
  • Acknowledgments
  • Purpose of this book
  • Introduction To VHDL
    • Golden Rules of VHDL
    • Tools Needed for VHDL Development
  • VHDL Invariants
    • Case Sensitivity
    • White Space
    • Comments
    • Parentheses
    • VHDL Statements
    • if, case and loop Statements
    • Identifiers
    • Reserved Words
    • VHDL Coding Style
  • VHDL Design Units
    • Entity
    • VHDL Standard Libraries
    • Architecture
    • Signal and Variable Assignments
    • Summary
    • Exercises
  • VHDL Programming Paradigm
    • Concurrent Statements
    • Signal Assignment Operator ``<=''
    • Concurrent Signal Assignment Statements
    • Conditional Signal Assignment when
    • Selected Signal Assignment with select
    • Process Statement
    • Summary
    • Exercises
  • Standard Models in VHDL Architectures
    • Data-flow Style Architecture
    • Behavioral Style Architecture
    • Process Statement
    • Sequential Statements
      • Signal Assignment Statement
      • if Statement
      • case Statement
    • Caveats Regarding Sequential Statements
    • Summary
    • Exercises: Behavioral Modeling
  • VHDL Operators
    • Logical Operators
    • Relational Operators
    • Shift Operator
    • Other Operators
    • Concatenation Operator
    • Modulus and Remainder Operators
    • Review of Almost Everything Up to Now
    • Using VHDL for Sequential Circuits
    • Simple Storage Elements Using VHDL
    • Inducing Memory: Data-flow vs. Behavioral Modeling
    • Important Points
    • Exercises: Basic Memory Elements
  • Finite State Machine Design Using VHDL
    • VHDL Behavioral Representation of FSMs
    • One-Hot Encoding for FSMs
    • Important Points
    • Exercises: Behavioral Modeling of FSMs
  • Structural Modeling In VHDL
    • VHDL Modularity with Components
    • Generic Map
    • Important Points
    • Exercises: Structural Modeling
  • Registers and Register Transfer Level
    • Important Points
    • Exercises: Register Transfer Level Circuits
  • Data Objects
    • Types of Data Objects
    • Data Object Declarations
    • Variables and Assignment Operator ``:=''
    • Signals vs. Variables
    • Standard Data Types
    • User-Defined Types
    • Commonly Used Types
    • Integer Types
    • signed and unsigned Types
    • std_logic Types
    • Important Points
  • Looping Constructs
    • for and while Loops
      • for Loops
      • while Loops
      • Loop Control: next and exit Statements
  • Standard Digital Circuits in VHDL
    • RET D Flip-flop - Behavioral Model
    • FET D Flip-flop with Active-low Asynchronous Preset - Behavioral Model
    • 8-Bit Register with Load Enable - Behavioral Model
    • Synchronous Up/Down Counter - Behavioral Model
    • Shift Register with Synchronous Parallel Load - Behavioral Model
    • 8-Bit Comparator - Behavioral Model
    • BCD to 7-Segment Decoder - Data-Flow Model
    • 4:1 Multiplexer - Behavioral Model
    • 4:1 Multiplexer - Data-Flow Model
    • Decoder
  • Appendix VHDL Reserved Words
  • Appendix Standard VHDL Packages
    • IEEE Standard Libraries
    • Non-standard Libraries
  • Appendix VHDL Reference Cards
  • Appendix Contributors to This Book
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